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[Crack Hack] rom_des.zip

Description: DES 加密算法的VHDL和VERILOG 源程序及其TESTBENCH。
Platform: | Size: 30494 | Author: | Hits:

[Embeded-SCM Develop]  148个verilog hdl小程序（有很多testbench）——.rar

Description:
Platform: | Size: 55801 | Author: | Hits:

[Other resource] ADPLL

Description: verilog ADPLL file with testbench.v
Platform: | Size: 25639 | Author: 79979 | Hits:

[Other resource] usb1_funct

Description: usb1.1的verilog源代码。以及其测试仿真文件，现在很难找其测试文件既testbench-usb1.1 verilog the source code. Simulation and test document, and now it is very difficult to find the paper test testbench
Platform: | Size: 52033 | Author: liuzefu | Hits:

[Embeded-SCM Develop] 16bit_booth_multiplier_STG

Description: verilog程序，实现两个16bit数乘法，采用booth算法，基于状态机实现，分层次为datapath和controller两个子模块，testBench测试通过-verilog procedures, two 16bit multiplication, the algorithm used booth. Based on the state machine achieved at different levels for datapath controller and two sub-modules, testBench the test
Platform: | Size: 2241 | Author: seiji | Hits:

[Other resource] hdb3_verilog

Description: modelsim工程，用verilog实现的HDB3编码，以及测试程序testbench-modelsim works with verilog realized HDB3 coding, and testing procedures testbench
Platform: | Size: 23041 | Author: chengroc | Hits:

[Other resource] oc8051

Description: 8051的verilog实现，内附testbench,c语言调试程序-8051 verilog achieve, enclosing testbench, c language debugging procedures
Platform: | Size: 1227477 | Author: wutailiang | Hits:

[Other resource] FIFO_v

Description: FIFO的verilog实现，内附testbench和文档说明-FIFO verilog achieve, enclosing testbench and documentation shows
Platform: | Size: 175386 | Author: wutailiang | Hits:

[Other resource] s_fifo

Description: 一个verilog语言描写的同步fifo,包括:Fifo using declared registers for storage和Fifo using (model of) standard memory chip for storage.两种方式,包含testbench
Platform: | Size: 2279 | Author: 彭帅 | Hits:

[Other resource] dac

Description: DAC converter design with Verilog code and testbench
Platform: | Size: 527384 | Author: 田磊 | Hits:

[Other resource] ArtofWritingTestBenches

Description: Art of Writing TestBenches：极经典的testbench书写入门书籍，能够让初学者在短时间内掌握testbench的书写步骤，对testbench有一个初步的认识，这是一个verilog方面的，没找到verilog就选了开发环境为vhdl
Platform: | Size: 97994 | Author: 侯浩 | Hits:

[Other resource] crc16_ccitt

Description: crc_table.c is for reset seed( 0000 ) crc_table_1.c is for reset seed( ffff) CRC16_D8_m.v is a verilog module of byte paralle crc. CRC16_D8_m_tb.v is the testbench file of above module.
Platform: | Size: 3242 | Author: 樊文杰 | Hits:

[Other resource] DCT

Description: altera fpga verilog 设计的基于查找表的DCT程序及zigzag扫描程序，已经过matlab 和modelsim 验证，文件中包含TESTBENCH ，直接可用
Platform: | Size: 15401328 | Author: alison | Hits:

[Other resource] flash接口控制_verilog

Description: flash接口控制器的VHDL以及verilog源代码和Testbench程序-flash interface controller VHDL and Verilog source code and procedures Testbench
Platform: | Size: 870604 | Author: 李楠 | Hits:

[VHDL-FPGA-Verilog] Writing_Efficient_Testbenches

Description: vhdl语言 和verilog hdl语言的测试程序编写- testbench for vhdl and verilog
Platform: | Size: 197632 | Author: kang | Hits:

[VHDL-FPGA-Verilog] i2c.tar

Description: 是个I2C软核，使用verilog和vhdl实现的，含有testbench。-this is soft core of I2C in verilog rtl and VHDL.
Platform: | Size: 702464 | Author: 杨力 | Hits:

[VHDL-FPGA-Verilog] DW8051_ALL

Description: 包中包括, DW8051完整的Verilog HDL代码 两本手册: DesignWare Library DW8051 MacroCell, Datasheet DesignWare DW8051 MacroCell Databook 三篇51论文: 基于IP 核的PSTN 短消息终端SoC 软硬件协同设计 Embedded TCP/ IP Chip Based on DW8051 Core 以8051为核的SOC中的万年历的设计 -DW8051 is designed by synopsys, and its instruction cycle is 4 clock, which lead to about 3 times faster than Intel 8051 with the same oscillator frequency. I writed ram, rom, some other perpherals such as DES, RNG, and its testbench, and it worked all right!
Platform: | Size: 1588224 | Author: myfingerhurt | Hits:

[VHDL-FPGA-Verilog] dct_parallel.tar

Description: paralel DCT hardware in verilog with testbench
Platform: | Size: 348160 | Author: victor | Hits:

[VHDL-FPGA-Verilog] uart_rx

Description: Verilog实现的RS232发送和接收程序，有完成的verilog代码，testbench等。(UART send and receive verilog code, including verilog source code, testbench etc.)
Platform: | Size: 452608 | Author: 66778899 | Hits:

[VHDL-FPGA-Verilog] W25Q80NE verilog Model

Description: SPI FLASH官方仿真模型方便modelsim testbench调试仿真(Official simulation model facilitates debugging and simulation)
Platform: | Size: 1673216 | Author: chengruiqi | Hits:
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